1. Field of the Invention
The present invention generally concerns the provision of electrically conductive (i) traces and (ii) pads on microminiature electronic components assembled and integrated in three-dimensional, monolithic form. Such monolithic multiple electronic components particularly include, but are not limited to, monolithic, buried-substrate, multiple ceramic capacitors (sometimes called "ceramic multiple capacitors").
The present invention more particularly concerns a way (i) in which electrical interconnection internal to the monolith may be made between the multiple electronic components of the monolith, and, also, (ii) by which external electrical connection to the monolith itself (and to selected electronic components therein) may be made. For example, the present invention particularly concerns multi-path electrical interconnections between, and external electrical connections to, (i) each of the multiple capacitors that are within a monolithic, buried-substrate, multiple ceramic capacitor and, also (ii) one or more electronic circuit components, namely: integrated circuit receivers and amplifiers that are usefully connected to and packaged compactly with, and externally to, the monolithic multiple capacitor.
Thus, to state again, the present invention concerns both internal and external electrical connections that re respectively within, and to, a monolithic, three-dimensional, electrical component.
The present invention still more particularly concerns a process of accurately making both (i) narrow conductive traces, and also (ii) integral wide conductive pads, on the multiple surfaces of a monolithic multiple electronic component, and the monolithic component so made. The multiple electronic component may again particularly be a buried-substrate multiple ceramic capacitor simultaneously that has and presents both (i) narrow traces for multi-path electrical connection to each of several capacitors that are within the multiple capacitor, and (ii) broad pads are suitable for reliable external electrical connection including by surface mounting. The external electrical connections may particularly be to one or more integrated electronic receivers and amplifiers that are used, when physically mounted and electrically connected together with the multiple capacitor, as microminiature hearing aids inserted in the external acoustic meatus, or ear canal.
2. Description of the Prior Art
2.1 The Structure of Monolithic Multiple Buried-Substrate Capacitors
A monolithic buried-substrate, or multiple buried-substrate, multiple capacitor is sometimes identified with the two words "substrate" and "capacitor" reversed, and is sometimes called a Buried Capacitor Substrate, or BCS. Howsoever called, BCSs accord significant size reduction to microelectronic applications. A BCS integrates capacitors, resistors and traces together into a thin, multi-layer, monolith which can be joined with integrated circuit ("IC") devices. Volumetric reductions over individual "chip" capacitor and/or resistor components of 50% to 75% are possible because the BCS both eliminates the air gaps between passive components and replaces the alumina substrate of traditional hybrids.
A BCS accords the freedom to mount one or more ICs directly onto itself (or perhaps even one on each side). The composite device so formed can then be attached to a ribbon lead, a larger hybrid, or a Multi Chip Module. The BCS is also compatible with flip chip IC designs, giving the most dense hybrids presently possible, circa 1995.
Substrate density and management of parasitic capacitances are the technological keys to BCS miniaturization. A BCS desirably uses the finest possible spacing for electrical connections around its edges (typically 0.020"), thus offering the greatest number of connections between an IC and the multiple capacitors that are buried within the BCS. Stray capacitance between these connections is preferably controlled by the unique castellation forming technique taught in the related U.S. Pat. No. 5,367,430 for a MONOLITHIC MULTIPLE CAPACITOR. Inside the BCS, multi-layer technologies are used. Stray capacitance between these layers is preferably controlled by the use of high and low K dielectrics in combination, as is taught in U.S. Pat. No. 4,419,714 to Locke. These techniques combine to maintain parasitic capacitance at low levels, and to give low coupled noise, between internal capacitors.
Conductive traces and/or pads are typically placed only upon a "top", and sometimes also a "bottom", surface of the BCS. These conductive traces and/or pads are the basis by which electrical connections to the BCS are made have. They have previously been formed by printing, particularly by screen printing and more particularly by silk screening.
Electrical connection to these various top and/or bottom surface printed conductive traces and pads can be made by soldering, various types of wire bonding, and/or flip-chip die attach. The BCS itself can be attached by soldering to either a larger hybrid, a Multi Chip Module, or a flexible ribbon cable. IC's and discrete components can be attached at one or another surfaces of the BCS. The conductive surface traces and pads are typically printed as 5 mil lines with 5 mil spacing, and in any pattern required to fit the application.
Electrical connection between the capacitors buried within the BCS and the printed circuit traces and pads upon its top and/or bottom surfaces are preferably made as a series of castellations along one or more sides of the BCS. The series of castellations provide selective electrical connection from the plates of capacitors within the body of the BCS to particular conductive traces and pads the top and/or bottom surfaces of the BCS. The castellations consist of metallized pads separated by 6 to 12 mil deep air gaps. A pitch 0.020 inches between castellations is possible while still retaining excellent solder reflow characteristics. These castellations are, again, the subject of related U.S. Pat. No. 5,367,430 for a MONOLITHIC MULTIPLE CAPACITOR.
A soldered connection to a castellation can provide a variety of electrical connections: 1) directly to the IC; 2) through a passive component and then to the IC; or 3) to the IC with a capacitor shunt to ground. In cases where an IC on each side of the BCS requires many I/O connections, a series of castellations can be made with 5 mil pads and 5 mil spaces.
BCS can be produced in a variety of sizes. A typical minimum size is 0.070 by 0.070 inches. The size of a BCS will usually be chosen based on capacitance values desired, the voltage rating, and internal space needed to control stray capacitance. Any sizes up to 1" by 1" and larger are possible, with maximum capacitance values near 10 .mu.f. Again, the actual capacitance value achieved depends on the voltage rating required.
Because a BCS contain non-symmetric buried plates, variation in surface flatness can be expected. Production techniques allow three controls of this irregularity. A BCS can be made so that the top surface is flat and the bottom surface contains all the irregularity. A BCS can be made so that the bottom surface is flat and the top surface contains all the irregularity. Finally, a BCS can be made so that the irregularity is averaged on both sides, so that it is equally absorbed by the top and bottom surfaces.
Internal conductor traces can be used to connect castellations on side surface of the BCS to castellations upon another side surface of the BCS. Usually this is needed when internal capacitor arrangements make conventional layouts impossible, or to accommodate existing IC pad locations. The layer of connective traces can be put in at any level within the BCS, depending on what is optimal for reducing stray capacitance.
Various designs of the internal plates of each buried capacitor within a BCS are possible. Capacitance value depends on the active area of each capacitor and the number of layers used.
It is possible to design one or more capacitors adjacent to an internal ground plane. By changing the position of connecting tabs, almost any connection configuration can be achieved.
Shielded capacitors are created by having a series of capacitor plates which are surrounded by two ground planes. This shielding can occur above and below the capacitor or along the edge of the BCS.
Coupling capacitors can be designed using a stack of individual opposing plates. Again, capacitance value depends on the number of layers and the active area of each chip.
In a typical BCS, capacitors are stacked in different levels within the BCS; one or more capacitors are built on each level, and each capacitor tabs out to a different castellation. Typically one castellation will connect to all internal ground planes.
Stray capacitance between different internal capacitors within the BCS is controlled by varying the distance between the capacitors on the same level or by varying the layer thickness between levels.
BESS are commonly made from any of NPO, X7R, and Z5U dielectrics. For ease of designing a substrate, the dielectrics can be thought of as capacitance achieved per unit area, given a normalized dielectric thickness.
For an area 0.1 inches on a side, at a dielectric thickness of 0.001 inches, typical BCS capacitance values are as follows:
______________________________________ Dielectric Capacitance per .01 inch square @ 1.0 mil thick ______________________________________ NPO 312.7 pF X7R 7417 pF ZSU 6,477 pF ______________________________________
2.2 The Use of, and the Previous Electrical Connection to, Monolithic Multiple Buried-Substrate Capacitors
Monolithic multiple buried-substrate capacitors--sometimes call BCS as in the previous subsection--contain, just as their name indicates, multiple capacitors within a single, monolithic, body. Monolithic multiple buried-substrate capacitors are typically electrically connected to, and useful in combination with, small, integrated, electronic devices, particularly including the amplifiers and receivers of hearing aids that are inserted in the external acoustic meatus, or ear canal. The substantial purpose of putting multiple buried-substrate capacitors within a single monolith is to save volume; otherwise a number of separate conventional "chip" capacitors could be conventionally employed.
The difficulty of making electrical connections to multiple buried-substrate capacitors are, however, multiplied by the number of such separate connections to be made. The difficulty of electrical connection is further aggravated by the typical microminiature size of a multiple buried-substrate capacitor--which is typically as small as 0.070".times.0.070".times.0.020" thickness--and by the commensurate microminiature size of the electronic devices (e.g., Ics) to which the multiple capacitor is connected.
The connected electronic devices--IC amplifiers and receivers and the like requiring connection to external capacitors for filtering purposes--are typically provided with leads.
It has been suggested to place holes, or bores, in the body of a multiple buried-substrate capacitor--including by process of laser drilling--and to then place the leads in the bores, thus attempting to make down-hole electrical connection with selected electrodes of the buried capacitors. This effort has essentially come to naught. In the first place, the hole placement, by laser drilling or otherwise, tends to displace the conductive material of the electrodes that are penetrated by the drilling down hole, leaving an insufficient amount of this conductive material at the walls of the bores at (and only at) the regions of the exposed down-hole electrodes so as to permit electrical connection to be reliably made to the electrodes. Moreover, and equally importantly, it is all but impossible to wick solder into the typically small drilled holes. Finally, any access to these holes is likely--should an electronic device (an IC) be mounted flush to the multiple capacitor as is commonly desired--severely impeded.
Accordingly, the typical previous electrical connection of leaded electronic devices--IC amplifiers and receivers and the like--to the several capacitors that are within the body of a multiple buried-substrate capacitor has been by (i) bringing the electrodes of the capacitors to some localized, pad, region on a surface of the multiple buried-substrate capacitor, and then (ii) hand soldering the leads of the electronic devices to these pads.
To say that this hand soldering work is delicate and painstaking, and therefore expensive, is an understatement. It is typically performed by dexterous women viewing their soldering operations though microscopes. Present difficulties in electrically connecting one microminiature component to another is one reason that very, very small electronic items such as hearing aids that fit within the external acoustic meatus, or ear canal tend to be expensive, costing several hundreds and even thousands of dollars U.S. circa 1995.
The previous manner of constructing the pad regions at the top surface of a multiple buried-substrate capacitor is itself quite intricate. The multiple buried substrate capacitor is, as previously explained, comprised of a number of patterned layers which constitute the plates and the intervening insulating layers of multiple capacitors. The plate layers are selectively brought to a side surface of the multiple buried-substrate capacitor, and are then commonly (although not necessarily) brought to the top surface of the multiple buried-substrate capacitor by various means.
In U.S. Pat. No. 4,419,714 for a LOW INDUCTANCE CERAMIC CAPACITOR AND METHOD FOR ITS MAKING issued Dec. 6, 1983, external connections are brought out to bus bars. These bus bars may be connected externally to select desired values of capacitance for a particular circuit. The bus bars also represent a common face. Solder balls are confined by a mask, or solder dam, that is made of a material that will not wet (i.e., stick to the solder ball). These solder balls are placed on the common face, and upon the bus bars, to facilitate soldered external electrical connection of the multiple buried-substrate capacitors to an external circuit. The mask is placed by conventional masking and etching techniques, preferably by the well-known lift-off process as defined in U.S. Pat. No. 4,004,044 to Franco, et al.
Notably, all this patterning is not part of production of the multilayered construction of the multiple buried-substrate capacitor itself. The multiple buried-substrate capacitor is produced by stacking multiple, normally some thirty to one hundred and more (30-100+) sheets, normally of the order of three inches to five inches square (3-5 in.sup.2), of ceramic material. These sheets are selectively patterned with conductive ink by process of printing. The composite assembly is compressed and heated to drive off an organic binder and sinter, or fuse, the powdered ceramic layers into a monolithic structure. All the external electrical connection(s), and particularly the patterned solder mask, are thus made after the structure has been sintered, or fused.
The essential difference as to when this patterning operation is done is simple. During the assembly process, what will become each individual multiple buried-substrate capacitor is typically arrayed with a very great number, typically 800+, typically identical multiple capacitors. All are printed at once. Once an individual multiple capacitor is sawed away--as it must be in order to place and side-surface conductive bus bars--then any printing or patterning on any surface of the multiple capacitor must be performed for on that multiple capacitor alone. Because each multiple capacitor is very small, its registration for patterning, and its subsequent patterning, are each very difficult.
In the U.S. Pat. No. 4,430,690 for a LOW INDUCTANCE MLC CAPACITOR WITH METAL IMPREGNATION AND SOLDER BAR CONTACT issued Feb. 7, 1984 ("MLC" is defined in the patent to mean "multilayered ceramic"), external connections are themselves selectively soldered to a plurality of solder bars to mount the capacitor(s) to a circuit board--as opposed to the solder bars themselves being selectively electrically connected.
Finally, in the related U.S. Pat. No. 5,367,430 for a MONOLITHIC MULTIPLE CAPACITOR a series of castellations along the side(s) of a multiple capacitor (which is the same as, and which is sometimes called, a Buried Capacitor Substrate, or BCS) serve to provide electrical connection from capacitors within the body of the multiple capacitor to conductive traces and pads on the top and/or bottom surfaces of the multiple capacitor. These castellations are established by saw-cutting slots in cured conductive ink. The conductive ink traces (as are separated by the saw-cut slots) terminate by "rolling over" for a slight distance onto the top and bottom surfaces of the multiple capacitor. Although the minute top and bottom surface edge regions where the conductive ink has "rolled over" the edge exhibit excellent solder characteristics, these minute and localized regions are distinctly (i) near the edges of the top and bottom surfaces of the multiple capacitor, only, (ii) are undesirably small, and, as such, (iii) are themselves and without more totally unadaptable to forming some arbitrary pattern of pads at which, and to which, some external component or circuit having a predetermined lead pattern may be connected.
According to the need to extend the minute and localized "roll over" regions of the conductive ink that is upon the sides of the multiple capacitor to the further, non-edge, regions of the top and/or bottom surfaces of the multiple capacitor, the related patent teaches the expansion and extension of these edge regions to other, further areas, by the patterning of conductive traces. These conductive traces were patterned and placed on a top (an/or a bottom) surface of the multiple capacitor by printing, normally by screen printing or a like process.
This patterned printing must be done after the conductive ink (if not also the saw-cut slots defining the castellations) is already upon the multiple capacitor, meaning that the multiple capacitor must have been separated (by sawing) from the many, many others (typically 800+ such identical others) with which it was manufactured. The printing is accordingly at a small scale on a work piece multiple capacitor of small size, and is both exacting and difficult.
Accordingly, all the prior art of which the inventors are aware, including their own related patent, teach of the electrical connection, and the selective connection, of the capacitors that are within a multiple buried-substrate capacitor by at least some electrical paths that are, at least in part, printed or otherwise patterned on a (commonly, top) surface of an individual multiple buried-substrate capacitor. This printing and patterning must be done after, and as a separate process from, the original production of the multiple buried-substrate capacitor as was performed by processes of stacking, and of selectively printing, multiple layers, and of sintering the multi-layer structure so formed. Accordingly, this printing has universally been done one microminiature multiple buried-substrate capacitor at a time--instead of the 800+ that are commonly built at once--in a fixture, and with yield losses that are commensurate with the intricacy of the task.
The printing is and patterning is normally with silver metal as opposed to, for example, gold or a metal from the platinum group, normally platinum of palladium. This is because of cost; silver offering the best electrical conductivity per unit cost.
2.3 Small Electrical Components Can Be Efficiently and Reliably Electrically Connected by Reflow Soldering, Including by Automation, And the Electrical Connection of Such Small Components to Monolithic Multiple Buried-Substrate Capacitors is Taught in a Related Predecessor Patent Application
Reliable and efficient electrical connection of small things may be realized by reflow soldering. Many electrical components from microminiature, chip, capacitors to multi-terminal integrated circuit flat packs are connected to printed circuit boards by this technique.
The related predecessor patent application Ser. No. 08/528,885 teaches the (i) printing and adhering patterned metal on the top and/or bottom surfaces of a multi-layer laid-up green ceramic wafers containing a typically large array of ceramic multiple capacitors, normally 800+ such capacitors, the (ii) dicing the wafer into ceramic multiple capacitors each of which has patterned surface metal, and the (ii) co-firing the ceramic multiple capacitors each with its patterned surface metal to produce conductive traces and pads on the top and/or bottom surfaces of the ceramic multiple capacitors.
The traces so created particularly support that electrical connection should be made to (later-formed) conductive traces, and conductive castellations, on the sides of the multiple capacitor (as such conductive castellations are taught in related predecessor U.S. Pat. No. 5,367,430), and through these conductive traces and castellations to the electrodes of buried-substrate capacitors that are located within the ceramic multiple capacitor.
The pads so created are typically arrayed in a "pin-grid" pattern. The pads support (i) surface mounting of the ceramic multiple capacitor (normally at its "bottom" surface), and also (ii) surface mounting of other electronic components, particularly including integrated circuit amplifiers and receivers, to the ceramic multiple capacitor (normally at and upon its "top" surface). Multiple electrical components may be mounted and electrically interconnected in tiers in three dimensions to the pads of the ceramic multiple capacitor at high density of both (i) physical components and (ii) electrical paths.
The printing typically transpires by silkscreening, normally upon a laid-up multi-layer green ceramic wafer that is highly accurately registered in position. The typical wafer is laid-up in patterned layers, typically 16+ such layers, of ceramic dielectric and metallization. A typical wafer is four inches 4" in diameter and contains 800+ separate devices each of which will ultimately become a ceramic multiple capacitor. Each ceramic multiple capacitor is itself a monolithic microminiature device that typically contains some 8+ buried-substrate capacitors.
The patterned metal is preferably a noble metal, more preferably gold or a member of the platinum group, and more particularly palladium or platinum. The patterned metal must in any case be able to maintain pattern integrity during the high temperatures of firing. Silver, as is commonly used to print conductive pads on diced and fired substrates in the prior art, is thus excluded.
The adhering of this metal is preferably by a glass frit that is chosen based on the temperature of firing. The preferred glass frit is suitable for a temperature range from 1000.degree. C. to 1400.degree. C.
Several advantages are realized.
First, only one printing operation needs be done (per major surface) on an entire water--instead of one printing conductive traces on each of the multitudinous individual multiple ceramic capacitors, one or a few at a time, after dicing and firing. Registration, and generally also patterning, accuracy is improved simultaneously that the alignment task is made much easier.
Second, the co-fired metal creates integral, durable, and precisely located traces and pads of uniform thickness and good quality.
Third, the wafer may be, and normally is, patterned on both its top and bottom surfaces, thus ultimately serving to make conductive traces and pads on both the top and the bottom surfaces of the ceramic multiple capacitors. The conductive traces commonly extend to the edges of the top and bottom surfaces where they are readily wetted by such side-surface solder lands as ultimately electrically connect to buried capacitors. Particularly when this side-surface solder is contained and channeled in closely spaced parallel castellations upon up to all four sides of a ceramic multiple capacitor--as is taught in related U.S. Pat. No. 5,367,430--very dense and numerous connections can be made. Six or more (6+) separate capacitors may typically be connected, and interconnected, in a monolithic multiple ceramic capacitor having dimensions as small as 0.070".times.0.070".times.0.020".
Meanwhile, those pads (which pads are normally at one terminus of the traces) that are commonly located on the "bottom" surface of the multiple ceramic capacitor permit and support precision surface mounting. The surface mounting may be by any of adhering with conductive adhesive, soldering, reflow soldering, gold wire bonding, aluminum wire bonding, flip-chip mounting, or die bonding, and is most commonly by use of conductive adhesives or solder. The surface mounting is may be to any of a printed circuit board, a flexible substrate, an alumina substrate, a multi-chip module, an electrical circuit, or another electrical component.
Less obvious than is the use of the bottom pads of the ceramic multiple capacitor for surface mounting, additional pads that are commonly located on the "top" surface of the multiple ceramic capacitor permit and support the mounting--including surface mounting again by use of both conductive adhesives and solder--of still other (generally microminiature) circuits and components to the multiple ceramic capacitor.
A complex physical and electrical interconnection in multiple "tiers" in three-dimensions may thus be created by essentially using the ceramic multiple capacitor, with its multiple dense connective pads and paths, as the "bedrock", or "glue" for all. Consider that a multiple ceramic capacitor is a commonly usefully connected to, and between, many other physically separate components in complex electronic assemblies, such as hearing aids. See, for example, the related predecessor patent application Ser. No. 08/528,856 now U.S. Pat. No. 5,657,199 for CLOSE PHYSICAL MOUNTING OF LEADED AMPLIFIER/RECEIVERS TO THROUGH HOLES IN MONOLITHIC, BURIED-SUBSTRATE, MULTIPLE CAPACITORS SIMULTANEOUS WITH ELECTRICAL CONNECTION TO DUAL CAPACITORS OTHERWISE TRANSPIRING, PARTICULARLY FOR HEARING AID FILTERS.